首页> 外国专利> Signal transmission circuit, signal reception circuit and signal transmission / reception circuit, signal transmission method, signal reception method, signal transmission / reception method, semiconductor integrated circuit and control method thereof

Signal transmission circuit, signal reception circuit and signal transmission / reception circuit, signal transmission method, signal reception method, signal transmission / reception method, semiconductor integrated circuit and control method thereof

机译:信号发送电路,信号接收电路和信号发送/接收电路,信号发送方法,信号接收方法,信号发送/接收方法,半导体集成电路及其控制方法

摘要

The present invention is intended to provide a receiving circuit that operates synchronously even if the transmitted clock signal is of a small width. The first differential clock signals UCLK and UXCLK of the small amplitude voltage based on the power supply potential and the second differential clock signals LCLK and LXCLK of the small amplitude voltage based on the ground potential are transmitted. The PMOS transistor P1 of the CMOS inverter circuit constituting the inverter circuit 72 as the signal receiving circuit receives the first differential clock signal as its gate electrode and the source electrode thereof and the NMOS transistor N1 receives the first differential clock signal as its gate And receives the second differential clock signal as an electrode and a source electrode. Therefore, when the potential of the differential clock signal changes, the potentials of the gate electrode and the source electrode of the transistors P1 and N1 transit in opposite directions to each other to be surely blocked. Therefore, a low consumption current can be obtained as the differential clock signal has a small amplitude.
机译:本发明旨在提供一种即使发送的时钟信号的宽度很小也能同步工作的接收电路。传送基于电源电位的小振幅电压的第一差分时钟信号UCLK和UXCLK以及基于接地电位的小振幅电压的第二差分时钟信号LCLK和LXCLK。构成反相器电路72作为信号接收电路的CMOS反相器电路的PMOS晶体管P1接收第一差分时钟信号作为其栅极和源极,NMOS晶体管N1接收第一差分时钟信号作为其栅极并接收第二差分时钟信号作为电极和源极。因此,当差分时钟信号的电势改变时,晶体管P1和N1的栅电极和源电极的电势沿彼此相反的方向过渡,从而被可靠地阻挡。因此,由于差分时钟信号具有小的幅度,所以可以获得低消耗电流。

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