Division architecture unit over finite field ??

摘要

PURPOSE: A dividing device on a finite field GF(2¬m) based on a binary extended GCD(Greatest Common Divisor) algorithm is provided to make an operation speed fast and reduce a chip area by forming the dividing device with a control logic, an RS-block, an SR-block, and a UV-block. CONSTITUTION: The RS-block(2) calculates a value of 'R' and 'S' of the algorithm, and transfers an output value to the control logic(1). The SR-block(3) shifts a both-direction register value to right depending on a state value. The UV-block(4) calculates the value of 'U' and 'V' of the algorithm, and transfers the values of 'ui' and 'vi' to the control logic. The control logic generates a control signal needed for each block in order to perform division.