Switches and modular, scalable method of distribution STAFF FAST ETHERNET NETWORK

摘要

1. u043cu043eu0434u0443u043bu044cu043du0430u00a0 u043cu0430u0441u0448u0442u0430u0431u0438u0440u0443u0435u043cu0430u00a0 architecture fast ethernet switch, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0, switch ethernet is designed in the form of many individually programmable on u0434u043du043eu043fu043eu0440u0442u043eu0432u044bu0445 modules u0441u0432u00a0u0437u0438 u0434u043bu00a0 access to the common distribution bus (10), with each u043eu0434u043du043eu043fu043eu0440u0442u043eu0432u044bu0439 module u0441u0432u00a0u0437u0438 contains;programmable microcontroller (1), a u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0 block access to the transmitting environment of ethernet (mac) containing a processor with a reduced set of commands (risc cpu) and;logical device (5) u0440u0430u0441u043fu0440u0435u0434u0435u043bu0435u043du0438u00a0 training data for processing in real time and transfer data Ethern addressed ports u043du0430u0437u043du0430u0447u0435u043du0438u00a0 training and entering the u043eu0434u043du043eu043fu043eu0440u0442u043eu0432u044bu0439 module u0441u0432u00a0u0437u0438.;2. fast ethernet switch architecture for p.1, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0 so that each individually programmable u043eu0434u043du043eu043fu043eu0440u0442u043eu0432u044bu0439 module u0441u0432u00a0u0437u0438 contains u0434u0432u0443u0445u043fu043eu0440u0442u043eu0432u044bu0439 buffer frames (4), constructed in such a way that the vd u0430u0438u043cu043eu0434u0435u0439u0441u0442u0432u043eu0432u0430u0442u044c, on the one hand, the programmable by a (1) and, on the other hand, the logical device (5) u0440u0430u0441u043fu0440u0435u0434u0435u043bu0435u043du0438u00a0 data, the kim, u043fu0440u0438u043du00a0u0442u044bu0439 a frame data u043eu0431u043du043eu0432u043bu00a0u0435u0442u0441u00a0,at least part of the transfer (the vector) in the buffer capacity (4) so as to be suitable u0434u043bu00a0 transfer through u0443u043fu043eu043cu00a0u043du0443u0442u0443u044e tire u0440u0430u0441u043fu0440u0435u0434u0435u043bu0435u043du0438 u00a0 data (10).;3. fast ethernet switch architecture for p.2, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0 that contains logical device (9) arbitration, organized so that it is decentralized and u0441u043eu0434u0435u0440u0436u0438u0442u0441u00a0 in each of the u0443u043fu043eu043cu00a0u043du0443u0442u044bu0445 individually programmable u043eu0434u043du043eu043fu043eu0440u0442u043eu0432u044bu0445 modules u0441u0432u00a0u0437u0438,with the device u0432u0437u0430u0438u043cu043eu0441u0432u00a0u0437u0430u043du043e with a corresponding one of the logic devices (5) u0440u0430u0441u043fu0440u0435u0434u0435u043bu0435u043du0438u00a0 training data u0434u043bu00a0 u043fu0440u0435u0434u043eu0441u0442u0430u0432u043bu0435u043du0438u00a0 access right. wood data to u0443u043fu043eu043cu00a0u043du0443u0442u043eu0439 u0440u0430u0441u043fu0440u0435u0434u0435u043bu0435u043du0438u00a0 data bus (10) according to the equitable distribution of access rights and u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0 numbering scheme signals based on erp tov or identification.;4. fast ethernet switch architecture for u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0 1, so that u0443u043fu043eu043cu00a0u043du0443u0442u044bu0439 programmable microcontroller has the opportunity to access u0434u043bu00a0 individually the u043fu0440u043eu0433u0440u0430u043cu043cu0438u0440u043eu0432u0430u043du0438u00a0 through the interface unit.;5. fast ethernet switch architecture for p.4, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0, u0443u043fu043eu043cu00a0u043du0443u0442u044bu0439 interface block u00a0u0432u043bu00a0u0435u0442u0441u00a0 interface rs - 232.;6. fast ethernet switch architecture for p.1, u043eu0442u043bu0438u0447u0430u044eu0449u0430u00a0u0441u00a0 that additionally contains u043fu0440u00a0u043cu043eu0439 interface u043fu0430u043cu00a0u0442u0438 (DMI (2), a dram (dynamic u0441u0432u00a0u0437u0430u043du043du044bu0439 with operational data storage device (3) u0434u043bu00a0 u043eu0441u0443u0449u0435u0441u0442u0432u043bu0435u043du0438 u00a0 u043fu0440u00a0u043cu044bu0445 of u043fu0430u043cu00a0u0442u044c - u043fu0430u043cu00a0u0442u044c and / or exchange u0443u043fu0440u0430u0432u043bu00a0u044eu0449u0438u043cu0438 data and / or information about the u0441u043eu0441u0442u043eu00a0u043du0438u0438 in case of failure in the logical device (5) u0440u0430u0441u043fu0440u0435u0434u0435u043bu0435u043du0438u00a0 cadres yes u043du043du044bu0445 or data bus (10).;7. method u0440u0430u0441u043fu0440u0435u0434u0435u043bu0435u043du0438u00a0 training data ethernet in the mode of "store - and - u043eu0442u043fu0440u0430u0432u043bu00a0u0442u044c" using modular scalable architecture individually programmable one the port modules u0441u0432u00a0u0437u0438, comprising the following operations:;ensuring the modular scalable architecture individually programmable u043eu0434u043du043eu043fu043eu0440u0442u043eu0432u044bu0445 modules u0441u0432u00a0u0437u0438 organized u0434u043bu00a0 internal distribution u043bu0435u043du0438u00a0 training data, in such a way that each port after admission, u0441u043eu0445u0440u0430u043du0435u043du0438u00a0 and verify data integrity is to compete for access to a high speed bus u0440u0430u0441u043fu0440u0435u0434u0435u043bu0435u043du0438u00a0 data according to a fair arbitration scheme.based on the numbering and identification of ports;the transfer of frame data to at least one output port for a certain number of cycles of the frame data, and;operation u043fu0440u0438u043du00a0u0442u0438u00a0 u0440u0435u0448u0435u043du0438u00a0 such that each output port independently decides, in accordance with the status of the output buffers. u043fu0440u0438u043du00a0u0442u044c or reject the other frame data.;8. method for u043eu0442u043bu0438u0447u0430u044eu0449u0438u0439u0441u00a0 p.7, however, that the number of cycles u0443u043fu043eu043cu00a0u043du0443u0442u044bu043c frame data u00a0u0432u043bu00a0u0435u0442u0441u00a0 one, and only one, regardless of the number of output ports, at the same time piece ongoing u0443u043fu043eu043cu00a0u043du0443u0442u044bu043c individually programmable u043eu0434u043du043eu043fu043eu0440u0442u043eu0432u044bu043c module u0441u0432u00a0u0437u0438.;9. way on p.7, in which the data frames received u0443u043fu043eu043cu00a0u043du0443u0442u044bu043c individually programmable u043eu0434u043du043eu043fu043eu0440u0442u043eu0432u044bu043c module u0441u0432u00a0u0437u0438, u043eu0431u0440u0430u0431u0430u0442u044bu0432u0430u044eu0442u0441u00a0 in real-time by fi u043bu044cu0442u0440u0430u0446u0438u0438 at least width strip, the size of the frame and the frame by u0443u043fu0440u0430u0432u043bu00a0u044eu0449u0435u0433u043e addresses process at the network level 2 (level access to the network - mac) with the use of u0437u043eu0432u0430u043du0438u0435u043c reduced set of commands.;10. method for u043eu0442u043bu0438u0447u0430u044eu0449u0438u0439u0441u00a0 p.9, so that u0443u043fu043eu043cu00a0u043du0443u0442u044bu0439 u0443u043fu0440u0430u0432u043bu00a0u044eu0449u0438u0439 process u00a0u0432u043bu00a0u0435u0442u0441u00a0 u0438u0437u043cu0435u043du00a0u0435u043cu044bu043c in u0437u0440u0435u043du0438u00a0 volume filtered by the rechargeable u043au043eu043du0444u0438u0433u0443u0440u0430u0446u0438u043eu043du043d s parameters.;11. method for u043eu0442u043bu0438u0447u0430u044eu0449u0438u0439u0441u00a0 p.7, so that at least one of the u0443u043fu043eu043cu00a0u043du0443u0442u044bu0445 individually programmable u043eu0434u043du043eu043fu043eu0440u0442u043eu0432u044bu0445 modules u0441u0432u00a0u0437u0438 may be eligible for special the configuration tables before and / or during the time of the u0434u043bu00a0 u0432u044bu043fu043eu043bu043du0435u043du0438u00a0 monitoring the data stream to provide filtering and taking some training data dr. u043bu00a0 data flow analysis.;12. way on any of the preceding paragraphs, u043eu0442u043bu0438u0447u0430u044eu0449u0438u0439u0441u00a0 so that any required value u043fu0435u0440u0435u043au043bu044eu0447u0435u043du0438u00a0, which is less than a predetermined time, u043eu043fu0440u0435u0434 u0435u043bu00a0u0435u0442u0441u00a0 only length of off line individually programmable u043eu0434u043du043eu043fu043eu0440u0442u043eu0432u043eu0433u043e u043cu043eu0434u0443u043bu00a0 u0441u0432u00a0u0437u0438.;13. method for u043eu0442u043bu0438u0447u0430u044eu0449u0438u0439u0441u00a0 p.12, so that at least one individually programmable u043eu0434u043du043eu043fu043eu0440u0442u043eu0432u044bu0439 u0441u0432u00a0u0437u0438 module configured u0434u043bu00a0 u0432u044bu043fu043eu043bu043du0435u043du0438u00a0 at least one function u0430u0434u043cu0438u043du0438u0441u0442u0440u0438u0440u043eu0432u0430u043du0438u00a0 / u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0.;14. method for p.13, u043eu0442u043bu0438u0447u0430u044eu0449u0438u0439u0441u00a0 u0443u043au0430u0437u0430u043du043du0430u00a0 so that at least one u0444u0443u043du043au0446u0438u00a0 u0430u0434u043cu0438u043du0438u0441u0442u0440u0438u0440u043eu0432u0430u043du0438u00a0 / u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0 u043eu0441u0443u0449u0435u0441u0442u0432u043bu00a0u0435u0442u0441u00a0 simple u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0 network protocol (snmp) and / or base d u0430u043du043du044bu0445 u0443u043fu0440u0430u0432u043bu0435u043du0438u00a0 (MIB) u0434u043bu00a0 u043fu0440u0435u0434u0441u0442u0430u0432u043bu0435u043du0438u00a0 access to information about the architecture of ethernet switch, u043eu0431u0435u0441u043fu0435u0447u0438u0432u0430u00a0 relevant network address and the level of u043fu0440u0438u043bu043eu0436u0435u043du0438u00a0 ( therefore u0434u043bu00a0 u0443u0440u043eu0432u043du00a0 network (7).accessible through any individually programmable u043eu0434u043du043eu043fu043eu0440u0442u043eu0432u044bu0439 module u0441u0432u00a0u0437u0438.