Addition circuit for signals at input of quantising circuit, e.g. sigma-delta modulator circuit, such as used in wideband data transmission systems, comprising storage capacitors and switch

摘要

Addition circuit comprises two capacitors (21,22) and switches (11,12) and is so set-up that, during first clock phase, each of signals (V1,2) to be added is stored in corresponding capacitor by its charging. During second clock phase, capacitors are parallel-connected by switches for charge equalising between capacitors. Thus after charge equalising, gradually diminishing voltage forms output signal of addition circuit, with voltage diminishing up to scaling factor corresponding to sum of signals to be added. Independent claims are included for sigma-delta modulator circuit.