Cache - storage device for a microprocessor system with a cache - memory with an asynchronous data path

摘要

Cache - memory means (17) for a microprocessor system with a with a cpu - bus (14), which is coupled to the cpu (10), wherein the cpu - bus (14) in synchronism with a cpu - clock is a main memory, a coupled with the main memory and asynchronously with respect to the cpu - cyclically operating memory (15) and a cache - memory - subsystem (12, 13, 18), wherein the cache - memory - subsystem (12, 13, 18) the cache - memory means (17), and the cache - memory means (17) is executed as an integrated circuit, comprising:a cache - memory matrix (22) for storing data of a predetermined data lines length;a with the cpu - bus (14) coupled to the cpu - bus - interface (20, 21, 23) with a cpu - control device (21) and a cpu - buffer (20) for transferring data to and from the cpu - bus (14), wherein the cpu - buffer (20) with the cache - memory matrix (22) is coupled, wherein data with the predetermined data lines length with only one access to the cpu - buffer and transmitted from the cpu - buffer in sections to the cpu - bus (14) are multiplexed,a to said memory (15) coupled memory - interface with at least one buffer memory..