首页> 外国专利> Clock adjusting process for computer, involves replacing original adjustment value of logic control unit by frequency adjustment value previously stored in memory unit, if signal output of basic input/output system is irregular

Clock adjusting process for computer, involves replacing original adjustment value of logic control unit by frequency adjustment value previously stored in memory unit, if signal output of basic input/output system is irregular

机译:计算机的时钟调整过程,如果基本输入/输出系统的信号输出不正常,则用先前存储在存储单元中的频率调整值代替逻辑控制单元的原始调整值

摘要

The process involves initiating a booting up process for a computer, and detecting whether a signal output from a basic input/output system (BIOS) is irregular, by a detection control unit (230). An original adjustment value of a memory inside a logic control unit (220) is replaced by a frequency adjustment value previously stored in a memory unit (228), if the signal output of the BIOS is irregular. The booting up process is ended. An independent claim is also included for a device intended to adjust clock.
机译:该过程包括通过检测控制单元(230)启动计算机的启动过程,以及检测从基本输入/输出系统(BIOS)输出的信号是否不规则。如果BIOS的信号输出不规则,则用预先存储在存储单元(228)中的频率调整值代替逻辑控制单元(220)内的存储器的原始调整值。启动过程结束。对于旨在调节时钟的设备也包括独立权利要求。

著录项

  • 公开/公告号FR2868563A1

    专利类型

  • 公开/公告日2005-10-07

    原文格式PDF

  • 申请/专利权人 GIGA-BYTE TECHNOLOGY CO.LTD;

    申请/专利号FR20040050622

  • 发明设计人 CHANG YEN SHENG;

    申请日2004-03-30

  • 分类号G06F1/04;G06F11/07;

  • 国家 FR

  • 入库时间 2022-08-21 21:58:15

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