A comparator with isolatable inputs for reduced noise in a sub-ranging ADC

摘要

The higher order section of a sub-ranging ADC comprises a set of comparators coupled to an input line 6 and respective taps 7,8 on a resistive reference chain 3. There are no sampling capacitors, which reduces the capacitive load on the sample and hold circuit 2. To prevent amplifier noise feeding back to the input signal and thereby reducing the accuracy of lower order comparators, the inputs to each of the amplifiers in the higher order section are isolated by opening series switches and closing a shunt switch across the inputs to each amplifier in the high-order section (SW9, SW10, SW11, figures 2,3) when the lower-order section is operating. To reduce the effective input offset voltage, the gain of the second stage of each comparator may be reduced (23 in figures 2 to 5) during the non-comparing clock phase.