It is brief in constituting the memory cell and the relation channel effect reduction manner

摘要

According to one edge strip of this invention, production manner of floating gate die memory array the 1st source field (116,216,316) and is provided between the 2nd source field, (118,218) in order to make the trench expose (128,228) which stipulates the side wall (150,250) of the substrate (258,358), includes the process (404) which removes the dielectric from the isolation region (110) which is provided in the aforementioned substrate. This production manner furthermore includes the process (406) which injects the N die dopant which forms the N+ die field (252,352) the aforementioned 1st source field (116,216,316) and the aforementioned 2nd source field (118,218,318) and vis-a-vis with the aforementioned side wall (150,250). As for this production manner furthermore, it possesses with the process (408) which injects the P-type dopant which forms the P+ die field (256,356) which is provided in lower part of the aforementioned N+ die field (252,352) the aforementioned 1st source field (116,216,316) and the aforementioned 2nd source field (118,218) and vis-a-vis with the aforementioned side wall (150,250).