首页> 外国专利> METHOD OF RELIABILITY SIMULATION OF SEMICONDUCTOR DEVICE, AND RELIABILITY SIMULATOR

METHOD OF RELIABILITY SIMULATION OF SEMICONDUCTOR DEVICE, AND RELIABILITY SIMULATOR

机译:半导体装置的可靠性仿真方法及可靠性仿真器

摘要

PROBLEM TO BE SOLVED: To realize NBTI deterioration simulation and TDDB failure simulation which are very accurate and have wide application by creating an accurate NBTI (Negative Bias Temperature Instability) life model and TDDB (Time Dependent Dielectric Breakdown) life model and using them.;SOLUTION: When performing the reliability simulation of a semiconductor device based on the estimated value of the NBTI deterioration of a MOS transistor constituting the semiconductor device, a parameter Age which indicates an amount of accumulated NBTI stress with respect to the MOS transistor is calculated by a model expression expressed by Age=C ∫[(Ih/Area)m]dt, where Ih is a hole current in the gate insulation film of the MOS transistor, Area is a gate area of the MOS transistor, t is NBTI stress time, m is a model parameter, and C is a proportional constant.;COPYRIGHT: (C)2006,JPO&NCIPI
机译:解决的问题:通过创建精确的NBTI(负偏压温度不稳定性)寿命模型和TDDB(时变介电击穿)寿命模型并使用它们,以实现非常准确并具有广泛应用的NBTI劣化模拟和TDDB故障模拟。解决方案:当基于构成半导体器件的MOS晶体管的NBTI劣化的估计值执行半导体器件的可靠性仿真时,参数Age表示相对于MOS晶体管的NBTI应力累积量,通过由Age = C∫ [((Ih / Area) m ] dt)表示的模型表达式,其中Ih是MOS晶体管的栅极绝缘膜中的空穴电流,Area是MOS的栅极面积晶体管,t为NBTI应力时间,m为模型参数,C为比例常数。;版权所有(C)2006,JPO&NCIPI

著录项

  • 公开/公告号JP2006140284A

    专利类型

  • 公开/公告日2006-06-01

    原文格式PDF

  • 申请/专利权人 MATSUSHITA ELECTRIC IND CO LTD;

    申请/专利号JP20040327923

  • 发明设计人 KOIKE NORIO;

    申请日2004-11-11

  • 分类号H01L29/78;H01L21/336;G06F17/50;H01L21/00;H01L21/82;H01L21/822;H01L27/04;

  • 国家 JP

  • 入库时间 2022-08-21 21:53:14

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