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On-chip bus architectures with interconnected switch points, semiconductor devices using the same and methods for communicating data in an on-chip bus architecture
On-chip bus architectures with interconnected switch points, semiconductor devices using the same and methods for communicating data in an on-chip bus architecture
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机译:具有互连开关点的片上总线体系结构,使用其的半导体器件以及在片上总线体系结构中传输数据的方法
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摘要
An on-chip bus includes a plurality of switch points including first and second switch points, a plurality of inter-switch links including at least one inter-switch link coupled between the first switch point and the second switch point and configured to communicate data between the first switch point and the second switch point, and a plurality of functional block cores including first and second functional block cores coupled directly to the first switch point and configured to communicate data through the first switch point. Data transmitted from the first functional block core to the second functional block cores may pass through the first switch point without traversing any of the plurality of inter-switch links. Methods for communicating data on an on-chip bus are also disclosed.
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