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Low latency switch architecture for high-performance packet-switched networks
Low latency switch architecture for high-performance packet-switched networks
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机译:低延迟交换机架构,用于高性能分组交换网络
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摘要
A low latency switch architecture for high performance packet-switched networks which is a combination of input buffers capable of avoiding head-of-line blocking and an internal switch interconnect capable of allowing different input ports to access a single output simultaneously.
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