Specifying data timeliness requirement and trap enabling on instruction operands of a processor

摘要

A computer has its programs in instructions and operand descriptors to specify the operands of the instructions. Apparatus for specifying data timeliness requirements of individual pieces of data pointed by the instruction operands is described hereby. The data timeliness requirements range from the local memory (the memory in the computing system processing the instructions), to the need to have the most updated copy of the piece of data in a system through the network (external memory), to any copy of the piece of data from external memory in a system through network. In a computer system wherein data items (operands) are represented by operand descriptors that can comprise object numbers, addresses, data types and sizes, vector information and other relevant information concerning the operands, with two bits to identify if the timeliness requirement of data of the operand, and one-bit flag of trap enabling of the corresponding operand, to enable a trap when the operand is encountered during processing of the instruction. The trap will further divert various handlers to service the trap according to the codes or flags set in the Processor Status Register or Processor Control Register in the processor.