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Adaptive processor architecture incorporating a field programmable gate array control element having at least one embedded microprocessor core
Adaptive processor architecture incorporating a field programmable gate array control element having at least one embedded microprocessor core
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机译:包含具有至少一个嵌入式微处理器内核的现场可编程门阵列控制元件的自适应处理器体系结构
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摘要
A multi-adaptive processor element architecture incorporating a field programmable gate array (“FPGA”) control element having at least one embedded processor core and a pair of user FPGAs forming a user array is disclosed in conjunction with high volume dynamic random access memory (“DRAM”) and dual-ported static random access memory (“SRAM”) banks. In operation, the DRAM is “read” using its fast sequential burst modes and the lower capacity SRAM banks are then randomly loaded allowing the user FPGAs to experience very high random access data rates from what appears to be a very large virtual SRAM. The reverse also happens when the user FPGAs are “writing” data to the SRAM banks. These overall control functions may be managed by an on-chip DMA engine that is implemented in the control FPGA.
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