Scaleable architecture for multiple-port, system-on-chip ADSL communications systems

摘要

A multi-port communications system is described, which includes hardware based subsystems for performing both physical medium dependent operations and transport convergence operations on a data transmission. A software based subsystem performs other operations as needed. Both types of subsystems are shareable by the communications ports so as to reduce a total hardware requirement of a communications system. In addition, processing blocks within both subsystems are adapted to be multi-tasking, in that they can perform multiple operations for a receive/transmit task, or even a mixture of receive/transmit tasks. The subsystems are arrangeable in a logical/hybrid pipeline arrangement with a common memory to further maximize the flexibilty and configurability of a communications system.