首页> 外国专利> Cache system and method for controlling the cache system comprising direct-mapped cache and fully-associative buffer

Cache system and method for controlling the cache system comprising direct-mapped cache and fully-associative buffer

机译:高速缓存系统和用于控制包括直接映射高速缓存和全关联缓冲器的高速缓存系统的方法

摘要

A method is provided for controlling a cache system. The cache system to be controlled comprises a direct-mapped cache configured with a small block size, and a fully associative spatial buffer configured with a large block, which includes a plurality of small blocks. Where accesses to the direct-mapped cache and the fully associative buffer are misses, data of a missed address and data of adjacent addresses are copied to the large block in the fully associative spatial buffer according to a first-in-first-out (FIFO) process. Furthermore, if one or more small data blocks is accessed among its corresponding large block of data which is to be expelled from the fully associative buffer, the small block(s) accessed is copied to the direct-mapped cache.
机译:提供了一种用于控制高速缓存系统的方法。待控制的缓存系统包括配置有小块大小的直接映射缓存和配置有大块的全关联空间缓冲器,该大块包括多个小块。如果错过了对直接映射缓存和完全关联缓冲区的访问,则根据先进先出(FIFO),将丢失地址的数据和相邻地址的数据复制到完全关联空间缓冲区中的大块)过程。此外,如果在要从全关联缓冲器中排出的其对应的大数据块中访问一个或多个小数据块,则将所访问的小块复制到直接映射的高速缓存中。

著录项

  • 公开/公告号US7047362B2

    专利类型

  • 公开/公告日2006-05-16

    原文格式PDF

  • 申请/专利权人 SHIN-DUG KIM;JUNG-HOON LEE;

    申请/专利号US20030258074

  • 发明设计人 SHIN-DUG KIM;JUNG-HOON LEE;

    申请日2001-05-16

  • 分类号G06F12;

  • 国家 US

  • 入库时间 2022-08-21 21:43:12

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号