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Highly parallel structure for fast multi cycle binary and decimal adder unit
Highly parallel structure for fast multi cycle binary and decimal adder unit
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机译:高度并行的结构,用于快速多周期二进制和十进制加法器单元
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摘要
An adder circuit for adding two binary or two decimal operands A and B in which the carries are calculated directly from the input operands A and B without including the plus 6 or minus 6 operations into the carry calculation. For all timing critical functions the reduced input data set, i.e., valid decimal data can be used and the non-existing decimal numbers (10 to 15) need not be excluded by separate check logic any more. This reduces the complexity of the logic functions.
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