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Digital trigger filter for a real time digital oscilloscope

机译:实时数字示波器的数字触发滤波器

摘要

A real time DSO is equipped with a Digital Trigger Filter that performs high frequency rejection, low frequency rejection, AC and DC triggering. The Digital Trigger Filter includes first and second digitally implemented IIR (Infinite Input Response) Filters. A digitized Conditioned Input Signal is applied to the first IIR Filter. It has taps that provide the Trigger Signal outputs needed for high and low frequency rejection. The high frequency rejection output of the first ER Filter is essentially a low pass output (3 dB down at 50 KHz) and is also used as the digital input to the second IIR Filter, whose output is a much more aggressive suppression of high frequencies (3 dB down at 50 Hz). The AC Trigger Signal output is produced by subtracting the output of the second IIR filter from the original input to the entire Digital Trigger Filter, and the DC Trigger Signal output is simply the same as that original input. A MUX selects which Trigger Signal is applied to a Digital Trigger Comparator.
机译:实时DSO配备了数字触发滤波器,可以执行高频抑制,低频抑制,交流和直流触发。数字触发滤波器包括第一和第二数字实现的IIR(无限输入响应)滤波器。将数字化的条件输入信号应用于第一个IIR滤波器。它具有分接头,可提供高频和低频抑制所需的触发信号输出。第一个ER滤波器的高频抑制输出本质上是一个低通输出(在50 KHz下下降3 dB),还用作第二个IIR滤波器的数字输入,第二个IIR滤波器的输出是对高频的更加积极的抑制(在50 Hz下降低3 dB)。交流触发信号输出是通过从原始输入减去第二个IIR滤波器的输出到整个数字触发滤波器而产生的,直流触发信号的输出与原始输入完全相同。 MUX选择将哪个触发信号施加到数字触发比较器。

著录项

  • 公开/公告号US7072804B2

    专利类型

  • 公开/公告日2006-07-04

    原文格式PDF

  • 申请/专利权人 DENNIS J. WELLER;

    申请/专利号US20040952311

  • 发明设计人 DENNIS J. WELLER;

    申请日2004-09-28

  • 分类号G06F19/00;

  • 国家 US

  • 入库时间 2022-08-21 21:41:24

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