Low-cost high-speed multiplier/accumulator unit for decision feedback equalizers

摘要

A multiplier device for multiplying one of a discrete set of digital level values with a filter coefficient in a filter device implemented in a decision feedback equalizer including (i) a decoder device for receiving a discrete digital level value to be multiplied and for generating control signals according to the digital level value, (ii) an inverter circuit providing two parallel operations, each operation including multiplying the determined number by either +1/−1 in accordance with the control signals for generating two intermediate results, (iii) a multiplier circuit receiving the two intermediate results and providing respective parallel operations for multiplying a corresponding intermediate result by +1 or zero (0) in accordance with a control signal and generating further intermediate results, (iv) a logic circuit for shifting bits of one further intermediate result to effect a multiplication of one of the further intermediate output result with a discrete digital level value different than any of the original plurality of discrete digital level values, and, (v) an accumulator device for adding the results of the logic circuit shift multiplication with the further intermediate output result to obtain a final multiplication result. The multiplier device is implemented for performing convolution operations with the filter and generating filter outputs implemented for reducing inter-symbol-interference in a communication system. The multiplier device advantageously achieves the desired multiplications for convolution operations using less semiconductor real estate, and at a greater speed and less redundancy.