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Cycle slip framing system and method for selectively increasing a frame clock cycle to maintain related bits within the same parallel-output frame of a deserializer
Cycle slip framing system and method for selectively increasing a frame clock cycle to maintain related bits within the same parallel-output frame of a deserializer
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机译:用于有选择地增加帧时钟周期以将相关比特保持在解串器的相同并行输出帧内的周期滑动成帧系统和方法
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摘要
A system and method are provided for synchronizing a frame of related bits output from a deserializer to the related bits serially fed to the deserializer. Synchronization is achieved by overcoming a slip bit problem by selectively increasing the frame clock cycle during times in which the slip bit occurs. The deserializer is controlled by a clock generator that can include a counter which generates the frame clock. The counter can be asynchronously or synchronously reset, without any glitches occurring within the deserializer and, thus, avoiding any invalid bits output from the deserializer. The asynchronous reset forces the counter to a deterministic state, and the synchronous reset sets the counter to a valid state. In each instance, however, resets do not impart glitches to the deserializer and the deserializer output frame is maintained synchronous to related bits serially fed to the deserializer.
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