METHOD AND APPARATUS FOR DESIGN VERIFICATION USING EMULATION AND SIMULATION

摘要

A method and apparatus for combining emulation and simulation of a logicdesign. The method and apparatus can be used with a logic design that includesgate-leveldescriptions, behavioral representations, structural representations, or acombination thereof.The emulation and simulation portions are combined in a manner that minimizesthe time fortransferring data between the two portions. Simulation is performed by one ormoremicroprocessors while emulation is performed in reconfigurable hardware suchas fieldprogrammable gate arrays. When multiple microprocessors are employed,independentportions of the logic design are selected to be executed on the multiplesynchronizedmicroprocessors. Reconfigurable hardware also performs event detecting andschedulingoperations to aid the simulation, and to reduce processing time.