SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, DELTA-SIGMA MODULATION TYPE FRACTIONAL DIVISION PLL FREQUENCY SYNTHESIZER, RADIO COMMUNICATION DEVICE, DELTA-SIGMA MODULATION TYPE D/A CONVERTER

摘要

A fractional frequency divider (28) includes a latch (31) for holding frequency division data, a DELTA SIGMA modulator (33), a digital dither circuit (32) for receiving a digital input F representing fraction part of the frequency division data from the latch (31) and supplying a digital output alternately changing between F+k and F-k (where k is an integer) or a F value itself to the DELTA SIGMA modulator (33), and circuit means (34 through 38) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the DELTA SIGMA modulator (33). The digital dither circuit (32) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the DELTA SIGMA modulator (33) receives a particular F value (e.g., F=2n-1). IMAGE