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CLOCKTREE TUNING SHIMS AND SHIM TUNING METHOD

机译:时钟树调整码和调整码方法

摘要

A digital storage medium for storing electronic data for use with a clock tree design tool to design a clock distribution network within an integrated circuit. The electronic data implements a library of shim cells, wherein each of the shims cells represents a physical embodiment of a different clock driver cell such that all of the shim cells in the library are interchangeable in the clock distribution design without requiring any change in the placement or routing within the integrated circuit to maintain compliance with design requirements for the integrated circuit. Each cell within a library represents a structure that introduces a particular delay time in the clock signal. The library contains cells having a range of delays that span a range that is sufficiently large to deal with the range of clock skews typically encountered during integrated circuit design.
机译:一种数字存储介质,用于存储电子数据,以便与时钟树设计工具一起使用,以设计集成电路内的时钟分配网络。电子数据实现了一个匀场单元库,其中每个匀场单元代表了一个不同时钟驱动器单元的物理实施例,因此该库中的所有匀场单元在时钟分配设计中都可以互换,而无需更改布局集成电路内的布线或布线以保持对集成电路设计要求的遵守。库中的每个单元代表一种在时钟信号中引入特定延迟时间的结构。该库包含具有一定范围的延迟的单元,该范围的范围足够大以应对集成电路设计过程中通常遇到的时钟偏斜范围。

著录项

  • 公开/公告号EP1599893A2

    专利类型

  • 公开/公告日2005-11-30

    原文格式PDF

  • 申请/专利权人 TIMELAB CORPORATION;

    申请/专利号EP20040714104

  • 发明设计人 MANDRY JAMES E.;

    申请日2004-02-24

  • 分类号H01L21/00;

  • 国家 EP

  • 入库时间 2022-08-21 21:32:43

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