Method for reducing the number of coherency cycles within a directory-based cache coherency memory system utilizing a memory state cache

摘要

The present invention relates to a method for replacing entries within a state cache memory of a multiprocessor computer system. The computer system has, in addition to the state cache memory, a shared system memory, a plurality of data cache memories, a system of busses interconnecting the system memory with the data cache memories, and employs a centralised/distributed directory based cache coherency scheme for maintaining consistency between lines of memory within said shared system memory and the data cache memories.;The method establishes a default memory state of SHARED for lines of memory represented in the state cache memory. The system memory line state for a state cache entry associated with a line of memory stored in the shared memory and at least one data cache memory is read prior to its replacement. A castout operation updates the line of memory within the shared memory and assigns a data cache memory line state of SHARED to the line of memory in each data cache memory if the system memory line state is OWNED.