A SINGLE - CHIP ANALOG TO DIGITAL VIDEO DECODER WITH ON - CHIP VERTICAL BLANKING INTERVAL DATA SLICING DURING LOW - POWER OPERATIONS

摘要

A single-chip video decoder includes a primary data path for capturing and silicing vertical blanking interval information carried by a primary channel of video data received by a video decoder. Power control circuitry is operable during an inactive period of the video decoder to activate the primary data path during vertical blanking intervals of the received primary channel of video data for capturing and slicing the vertical blanking interval data; and to deactivate the primary data path between the vertical blanking interval and a subsequent vertical blanking interval of the received primary channel of video data to reduce power consumption. According to further inventive concepts, analog and/or digital circuitry which is unnecessary for capturing and slicing the vertical blanking information, including data paths processing secondary channels of video data, is deactivated during substantially the entire inactive period of the video decoder. In an additional embodiment, the input/output ports of the video decoder are set into a static state for substantially the entire inactive period.