APPARATUS FOR GENERATING A ON-CHIP NETWORK TOPOLOGY AND METHOD THEREFOR

摘要

An on-chip network topology generating apparatus and method are disclosed. By performing the reference code implemented by the design specification of the algorithm step, it analyzes the communication requirements between the IP modules, and generates a binary tree with the IP modules as the lowest child node based on the communication requirements between the IP modules. Then, among all cases where merging between the lower nodes connected to the predetermined intermediate node and the predetermined intermediate node of the binary tree is possible, the process of selecting a merge that minimizes the value of the cost function defined based on the area and the communication delay time is performed. Reorganize the tree by running up to the root node. This allows the creation of an on-chip network topology with minimal area and communication latency.;On-Chip Network Topology, IP Modules, Communication Requirements, Binary Trees