TEST VECTOR COMPRESSION METHOD USING XOR TREE

摘要

The invention column scanning is set to the circuit under test (CUT, circuit under test) (scan chain ) In the BIST (built-in self test) for generating test vectors in accordance with , the present invention relates to a method for compressing the test vectors by using the XOR tree seed merging . The method of the present invention , "do not care" bits by using the T _D setting a vector , by using the XOR tree , including the n XOR T _D step of reducing , by using a prefix bit compressing the seed vector (T _S vector ) and is composed of setting a T _NS vector .