Interdependent parallel processing hardware cryptographic engine providing for enhanced self fault-detecting and hardware encryption processing method thereof

摘要

The hardware encryption device for enhanced error detection interdependent self- parallel algorithm and its hardware encryption method starts the . The interdependent method of parallel processing hardware encryption device , the process using two or more hardware cipher engine for performing cryptographic operations in parallel by a symmetric algorithm , such as DES, even if the same error occurs in the same position as the final encryption result to detect errors that may prevent the leakage of confidential information before outputting . Therefore , a strong attack on the error , and the cryptographic operations is more than twice that fast effect does not repeat operation speed .