首页> 外国专利> A METHOD FOR SENSING A BIT LINE PROVIDING A CONSISTENT SENSING MARGIN INTERVAL REGARDLESS OF VARIATIONS IN AN EXTERNAL POWER VOLTAGE AND A MEMORY DEVICE THEREFOR

A METHOD FOR SENSING A BIT LINE PROVIDING A CONSISTENT SENSING MARGIN INTERVAL REGARDLESS OF VARIATIONS IN AN EXTERNAL POWER VOLTAGE AND A MEMORY DEVICE THEREFOR

机译:一种用于检测外部电源电压变化一致的保证金间隔的位线的方法及其存储器

摘要

The present invention is a sensing method having a bit line sensing margin time regardless of the change of the external voltage , and a uniform be to provide a memory device therefor , a bit line sensing method of the present invention to do this is a method for driving a semiconductor memory device having the memory cells connected to word lines and bit lines , the word line is driven by the external voltage generating a first control signal for activation ; And the driving voltage , and a core having a uniform , regardless of the bit line sensing margin time to changes in the external voltage , including the step of generating a second control signal for amplifying the potential of the first control input receiving a bit line signal features .
机译:本发明是一种具有与外部电压的变化无关的位线感测余量时间的感测方法,并且本发明的目的是提供一种用于其的存储器件,本发明的位线感测方法是用于驱动具有连接到字线和位线的存储单元的半导体存储装置,字线由外部电压驱动,产生用于激活的第一控制信号;并且驱动电压,以及具有均匀的铁心,不管位线感测到外部电压变化的余量时间,包括产生第二控制信号的步骤,用于放大接收位线信号的第一控制输入的电位特征 。

著录项

  • 公开/公告号KR100550632B1

    专利类型

  • 公开/公告日2006-02-10

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20030027684

  • 发明设计人 윤준열;

    申请日2003-04-30

  • 分类号G11C11/4091;

  • 国家 KR

  • 入库时间 2022-08-21 21:24:20

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