首页> 外国专利> ION-IMPLANTATION AND SHALLOW ETCHING TO PRODUCE EFFECTIVE EDGE TERMINATION IN HIGH-VOLTAGE HETEROJUNCTION BIPOLAR TRANSISTORS

ION-IMPLANTATION AND SHALLOW ETCHING TO PRODUCE EFFECTIVE EDGE TERMINATION IN HIGH-VOLTAGE HETEROJUNCTION BIPOLAR TRANSISTORS

机译:离子注入和浅蚀刻在高压异质结双极晶体管中产生有效的边缘终止

摘要

The semiconductor device while maintaining breakdown voltage as a theoretical limit or close to the semiconductor device 100 The method for improving edge termination (42) is provided at 100. The method includes using an ion implantation (40) generates the compensation region 140 around the semiconductor device 100, followed by etching by a wet chemistry includes forming a mesa 114 so 0.2~0.3 . The method, and easy to achieve nearly ideal electrical properties in a typical semiconductor device 100 and GaAs heterojunction bipolar transistor (HBT), such as edge termination in the device using the pn junction 42, a device manufactured by the edge 42 provides a new method. Grinding, sand casting, blur, or associated with the conventional mesa etching using a mask technique Burlingame chopping edge (edge beveling techniques) in place, in which the disclosed technology device (100) for generating a compensating ion implantation region 140 surrounding (40 ), and utilizes a wet chemical etching to form a shallow mesa (shallow mesa) (114).
机译:在维持击穿电压为理论极限或接近半导体器件100的同时的半导体器件。在100提供了用于改善边缘终止的方法(42)。该方法包括使用离子注入(40)在半导体周围生成补偿区域140器件100,然后通过湿化学法蚀刻包括形成台面114,因此为0.2〜0.3。该方法容易在典型的半导体器件100和GaAs异质结双极晶体管(HBT)中实现近乎理想的电性能,例如使用pn结42的器件中的边缘终止,由边缘42制造的器件提供了一种新方法。使用适当的掩模技术Burlingame切边(边缘倒角技术)进行打磨,砂铸,模糊化或与常规台面蚀刻相关联,其中所公开的技术设备(100)用于生成围绕(40)的补偿离子注入区140 ,并利用湿法化学蚀刻形成浅台面(浅台面)(114)。

著录项

  • 公开/公告号KR100610736B1

    专利类型

  • 公开/公告日2006-08-09

    原文格式PDF

  • 申请/专利权人

    申请/专利号KR20047010796

  • 发明设计人 몬테스매리씨.;휴쌔인타이어;

    申请日2004-07-09

  • 分类号H01L21/331;

  • 国家 KR

  • 入库时间 2022-08-21 21:23:17

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