1.u0440u0435u0446u0438u0440u043au0443u043bu00a0u0446u0438u043eu043du043du044bu0439 u043au043eu0440u0440u0435u043bu00a0u0442u043eu0440 u0440u0430u0437u0440u0435u0448u0435u043du0438u00a0 - u0440u0430u0437u043bu0438u0447u0435u043du0438u00a0 u0444u0430u0437u043eu043au043eu0434u043eu043cu0430u043du0438u043fu0443u043bu0438u0440u043eu0432u0430u043du043du044bu0445 signals includes first and second adder, a first and a second shift register, the first the second and the third switch, the cross u0441u0432u00a0u0437u0435u0439, block the rapid u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u043du0438u00a0 walsh block inverse cross u0441u0432u00a0u0437u0435u0439, block u0441u043eu0433u043bu0430u0441u043eu0432u0430u043du0438u00a0 with elemental dis u043au0440u0435u0442u043eu043c of two referencewith the entrance of the first u0441u0443u043cu043cu0430u0442u043eu0440u0430 u00a0u0432u043bu00a0u0435u0442u0441u00a0 first entrance and exit devices u00a0u0432u043bu00a0u0435u0442u0441u00a0 exits the second shift register, and a second entrance first amount the torah is connected with the exit of the first shift register, a first u0441u0443u043cu043cu0430u0442u043eu0440u0430 is connected with the entrance of the first shift register, which are connected with the line reaches exits the first concerned the entrance system.n exits which are connected with a cross u0441u0432u00a0u0437u0435u0439, n exits which are connected with the rapid u043fu0440u0435u043eu0431u0440u0430u0437u043eu0432u0430u043du0438u00a0 walsh, n outputs which are connected to the block om backward cross u0441u0432u00a0u0437u0435u0439, n exits which are connected with the second u043au043eu043cu043cu0443u0442u0430u0442u043eu0440u043eu043c, two way which are connected with the respective inputs of u0441u043eu0433u043bu0430u0441u043eu0432u0430u043du0438 u00a0 with simple u0434u0438u0441u043au0440u0435u0442u043eu043c of two referencetwo way which are connected with the respective inputs of the system, which, in turn, is connected to the first, second u0441u0443u043cu043cu0430u0442u043eu0440u0430 entrance, exit u043au043eu0442u043eu0440u043eu0433 on the entrance of the second shift register is connected to the second shift register, the output is connected to the second gate, second u0441u0443u043cu043cu0430u0442u043eu0440u0430.;2. u0440u0435u0446u0438u0440u043au0443u043bu00a0u0446u0438u043eu043du043du044bu0439 u043au043eu0440u0440u0435u043bu00a0u0442u043eu0440 u0440u0430u0437u0440u0435u0448u0435u043du0438u00a0 - u0440u0430u0437u043bu0438u0447u0435u043du0438u00a0 u0444u0430u0437u043eu043au043eu0434u043eu043cu0430u043du0438u043fu0443u043bu0438u0440u043eu0432u0430u043du043du044bu0445 signals on p.1 is composed of a block u0441u043eu0433u043bu0430u0441u043eu0432u0430u043du0438u00a0 with simple u0434u0438u0441u043au0440u0435u0442u043eu043c of two reference plane which contains the first and the second shift register block u0441u043eu0433u043bu0430u0441u043eu0432u0430u043du0438 u00a0 with simple u0434u0438u0441u043au0440u0435u0442u043eu043c of two reference entrances which u00a0u0432u043bu00a0u044eu0442u0441u00a0 entrances block, first and second shift registers for one clock.the first and second u0441u0443u043cu043cu0430u0442u043eu0440u044b block u0441u043eu0433u043bu0430u0441u043eu0432u0430u043du0438u00a0 with simple u0434u0438u0441u043au0440u0435u0442u043eu043c duration in the two reference outputs which u00a0u0432u043bu00a0u044eu0442u0441u00a0 exits the block, a first register a shift register is connected to the entrance of the first shift on one count and first and second u0441u0443u043cu043cu0430u0442u043eu0440u0430 entrance and exit the second shift register is connected to the entrance of the second egr the shift for one clock, and the first in first u0441u0443u043cu043cu0430u0442u043eu0440u0430,the first and second shift registers at one clock are connected respectively with the second inputs of first and second u0441u0443u043cu043cu0430u0442u043eu0440u043eu0432.;3. u0440u0435u0446u0438u0440u043au0443u043bu00a0u0446u0438u043eu043du043du044bu0439 u043au043eu0440u0440u0435u043bu00a0u0442u043eu0440 u0440u0430u0437u0440u0435u0448u0435u043du0438u00a0 - u0440u0430u0437u043bu0438u0447u0435u043du0438u00a0 u0444u0430u0437u043eu043au043eu0434u043eu043cu0430u043du0438u043fu0443u043bu0438u0440u043eu0432u0430u043du043du044bu0445 signals on p.1 is composed of a cross u0441u0432u00a0u0437u0435u0439 which contains cross u0441u0432u00a0u0437u0438, which must be designed so that while the entrance u0444u043au043c signal, coded m - sequence u043eu0441u0443u0449u0435u0441u0442u0432u043bu00a0u0435u043cu043eu0433u043e procedure u0440u0435u0446u0438u0440u043au0443u043bu00a0u0446u0438u0438, u0441u0442u0440u043eu0431u0435 4n - 1 at the interval equal to its 2n.the weekend u0437u043du0430u0447u0435u043du0438u00a0 block cross u0441u0432u00a0u0437u0435u0439 coincided with one of the rows of the matrix walsh - hadamard (without the first row and first column).
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