A device that converts serial code 'Manchester 2' In parallel code

摘要

A device that converts "Manchester 2" serial code to a parallel code relates to computer engineering and is intended for receiving information transmitted by trusted ultrafast communication channels provided in sequential PSK code "Manchester-2" digit from 2 to 32 and decoding it into parallel code in real time. The technical result of the expected utility model is to expand the range of the bit of the received information. A device that converts code "Manchester 2" in a parallel code, consisting of a decoder block parallelization and 20 bit parallel registers wherein the first and second outputs of the decoder are connected to first and second inputs parallelizing unit, first and second outputs are connected to the first and the second register input, the input device is input decoder outputs - the first decoder output, the second output parallelizing unit and the register output, and parallelizing unit consists of two inverters, twenty-two elements 2 OR- NOT, twenty-two D-flip-flops and an element 3 NOR first inverter input is a first input parallelization unit, the first inverter output is connected to a first input of the first element 2-OR-NO, the output of which is connected to the data input of the first D-flip-flop, output of the second element 2 NOR is connected to the data input of the second D-flip-flop and the like. d., yield twenty-second member 2-OR-NO element is connected to the data input of the twenty-second D-flip-flop inverse output of the first D-flip-flop connected to the first input of the second element 2 NOR inv ersny output of the second D-flip-flop; connected to the first input of the third element 2 NOR, etc., inverse output twenty-first D-flip-flop is connected to the first input of the twenty-second member 2 NOR direct output of the first D-flip-flop is coupled to a second input of the 3- NOR inverse output twenty-second D-flip-flop connected to the first input of the 3-OR-NO element and the input of the second inverter, whose output is connected to the second inputs of all the elements 2 NOR clock inputs of D-flip-flops and a third element input 3-OR-NO elements are connected to the second input block of parallelization; direct outputs D-flip-flops of the second to twenty-first form output dvadtsatirazryadnuyu bus, which is the first output parallelization unit, the second output of which is the output element 3-OR-NO element, characterized in that the bit width parallel register is increased from 20 to 32 and a parallelizing schematic block diagram of the elements 12 is further introduced 2 NOR, D-flip-flops 12 and 32-bit address bus multiplexer so that the inverted output of the twenty-second D-flip-flop is connected to the first input of the twenty- the third element 2 NOR twenty-inverse output of the third D-flip-flop is connected to the first input of the twenty-fourth element 2 NOR, etc., thirty-inverse output of the third D-flip-flop is connected to the first input of the thirty-fourth element 2 OR -NOT, yield twenty-third member 2-OR-NO element is connected to the data input of the twenty-third D-flip-flop, etc., yield thirty fourth element 2-OR-NO element is connected to the data input of the thirty-fourth D-flip-flop, a second input of each newly element introduced 2-OR-NO element is connected to the output W cerned inverter; the clock input of each newly inputted D-flip-flop is connected to the second input parallelization block, inverse outputs of D-flip-flops with a third; thirty-fourth, respectively connected to the first, second, etc. before the thirty second information multiplexer inputs, whose output is connected to a first input of the 3-OR-NO element and the input of the second inverter, due to the newly introduced 12 D-flip-flops and 12 elements 2 NOR bit parallelizing unit output bus increased from 20 to 32, moreover, the multiplexer address bus input is the third input of the block of parallelization.