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connection and input / output resources r amp; t.; r programmable integrated logikschaltungseinrichtungen

机译:连接和输入/输出资源的研发。 r可编程集成逻辑控制器

摘要

A programmable logic integrated circuit device (10) has a plurality of regions (20) of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources (200a, 210a, 230a) may have what may be termed normal signal speed, while a smaller minor portion (200b, 210b, 230b) may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
机译:可编程逻辑集成电路器件(10)具有多个可编程逻辑区域(20),该多个可编程逻辑区域以这样的区域的多个相交的行和列布置在该器件上。在设备上提供互连资源(例如,互连导体,信号缓冲器/驱动器,可编程连接器等),以实现到区域,从区域和/或在区域之间的可编程互连。这些互连资源中的至少一些以两种形式提供,它们在架构上是相似的(例如,具有相似且基本平行的路由),但是具有明显不同的信号传播速度特性。例如,这种双形式互连资源的主要或较大部分(200a,210a,230a)可能具有正常信号速度,而较小的较小部分(200b,210b,230b)可能具有明显更快的信号速度。 。次级(例如,时钟和清除)信号分配也可以得到增强,输入/输出电路和设备上相邻或附近逻辑模块之间的级联连接也可以得到增强。

著录项

  • 公开/公告号DE20023829U1

    专利类型

  • 公开/公告日2006-08-31

    原文格式PDF

  • 申请/专利权人 ALTERA CORP. SAN JOSE CALIF. US;

    申请/专利号DE2000223829U

  • 发明设计人

    申请日2000-03-02

  • 分类号H03K19/177;

  • 国家 DE

  • 入库时间 2022-08-21 21:21:02

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