Data memory uses a delay locked loop to provide reliable data transmission in an unstable environment having such as temperature swings

摘要

The memory (3) has a coupled interface (2) that handles data (D2) that is synchronised using clock signals (CLK,RDT). A delay locked loop, DLL, circuit (20) determines the optimal sampling point of the read data based upon comparison of the clock signals. A register circuit (11) is connected with the interface and this receives the delayed clock signal (CLK2).