Multithread processor, has synchronizing unit with logic circuit, which generates context switching signal with receipt of loading cycle indication flag having positive logical signal level and with validity signal having negative level

摘要

The processor has a synchronization unit (6) storing related context identification (ctxi) and destination register identification. The identifications are synchronized, buffed and transferred to a pipeline stage (9). The unit (6) has a logic circuit, which generates a context switching signal (css) with a receipt of a loading cycle indication flag having a positive logical signal level and a validity signal having a negative level. An independent claim is also included for a method for operating a multithread processor with synchronization of an instruction flow with an associated data flow and with generation of a memory triggered context switching signal.