Memory system has control circuit that delays refresh of target block, reads requested information from main memory and transfers target memory block to cache memory, when refresh start signal is enabled and read signal is received

摘要

A control circuit delays refresh of target block, reads requested information from main memory and transfers the target memory block to cache memory, when refresh start signal is enabled and read signal is received. The read and refresh of target block are performed without write back from cache to main memory, when cache memory does not store the target block, and data in cache is not valid. An independent claim is also included for method for operating memory system.