A differential voltage sense circuit has a fuse placed in one upper leg of a resistance bridge while the remaining upper leg (sense leg) employs a resistor constructed of doped poly or poly silicide or constructed of the doped silicon that forms the N-well or P-well in CMOS process. The lower legs each have a switch selected from a pair of matched switches. A comparator, latch and combinational logic sense the state of the fuse in the resistance bridge and latch the state information before the switches can operate to stop the flow of current in the resistance bridge. The differential voltage sense circuit can operate at low voltage levels compatible with advanced CMOS processes.
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