Generating two synchronisation pulses when two clock signals with different frequencies have coincident edges, to aid data transfer between clock domains

摘要

This invention concerns the generation of synchronisation pulses which are suitable for controlling data transfer between first circuitry (103A, Fig. 1) disposed in a first clock domain and second circuitry (103B, Fig. 1) disposed in a second clock domain. A sync circuit portion 900 receives a valid edge signal (edge_valid) indicative of coincident edges between a first clock signal (108, Fig. 1) of the first domain and a second clock signal (106, Fig. 1) of the second domain. Preferably the sync circuit also has a ratio input which indicates the frequency relationship between the two clock signals. The sync circuit generates a start sync signal centred on the coincident edges. The start sync signals triggers first and second sync generators 902, 904. The first sync generator generates synchronisation pulses (sync_1) in the first clock domain and the second sync generator generates synchronization pulses (sync_c) in the second clock domain.