Being the trench capacitor which was padded to the production manner of the DRAM electrolysis cell and the DRAM electrolysis cell and the production mannered null semiconductor substrate of the integrated circuit which possesses

摘要

A DRAM array having a DRAM cell employing vertical transistors increases electrical reliability and reduces bitline capacitance by use of an asymmetric structure in the connection between the wordline and the transistor, thereby permitting the use of a wider connection between the wordline and the transistor electrode and using the wordline as an etch stop to protect the transistor gate during the patterning of the wordlines.