首页> 外国专利> MACRO ARRANGEMENT DESIGN DEVICE WITH CONSIDERATION GIVEN TO DENSITY, PROGRAM, AND DESIGN METHOD

MACRO ARRANGEMENT DESIGN DEVICE WITH CONSIDERATION GIVEN TO DENSITY, PROGRAM, AND DESIGN METHOD

机译:考虑到密度,程序和设计方法的宏布置设计设备

摘要

PROBLEM TO BE SOLVED: To provide a pattern density check program, its device, and its method for calculating a pattern density for each layer from a layout of one chip including a scribe frame and finding a pattern density error early for reduction in occurrence of a return process and in a TAT.;SOLUTION: This pattern density check program makes a computer execute a first step S1 and a second step S3. In the first step S1, mask data 101 are read into the computer having a storage part storing chip data for a pattern density check objective chip and its mask data, and from the mask data 101, a scribe frame model having a data rate of the scribe frame for one chip of the density check objective chip is generated. In the second step S3, The chip data 102 are read, and density check for one chip is carried out based on a combination of the chip data and the scribe frame model.;COPYRIGHT: (C)2007,JPO&INPIT
机译:解决的问题:提供一种图案密度检查程序,其装置及其方法,用于从包括划片框的一个芯片的布局中计算出每一层的图案密度,并及早发现图案密度误差,以减少出现图案缺陷的可能性。解决方案:该图案密度检查程序使计算机执行第一步S1和第二步S3。在第一步骤S1中,将掩模数据101读入具有存储用于图案密度检查目标芯片的芯片数据及其掩模数据的存储部分的计算机中,并且从掩模数据101中,将具有生成密度检查目标芯片的一个芯片的划片框架。在第二步骤S3中,读取芯片数据102,并且基于芯片数据和划片框架模型的组合来对一个芯片进行密度检查。;版权所有:(C)2007,JPO&INPIT

著录项

  • 公开/公告号JP2006344176A

    专利类型

  • 公开/公告日2006-12-21

    原文格式PDF

  • 申请/专利权人 NEC ELECTRONICS CORP;

    申请/专利号JP20050171675

  • 发明设计人 YAMAGUCHI AYANO;

    申请日2005-06-10

  • 分类号G06F17/50;H01L21/82;

  • 国家 JP

  • 入库时间 2022-08-21 21:10:29

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