首页> 外国专利> MULTI-PROCESSOR SYSTEM, PREFETCH REQUEST CONTROL METHOD TO BE USED FOR THE SAME AND ITS PROGRAM

MULTI-PROCESSOR SYSTEM, PREFETCH REQUEST CONTROL METHOD TO BE USED FOR THE SAME AND ITS PROGRAM

机译:多处理器系统,用于其的预取请求控制方法及其程序

摘要

PPROBLEM TO BE SOLVED: To provide a multi-processor system for reducing main storage access frequency, and for reducing the DA access frequency of a request agent, and for reducing the data transfer frequency of a system interface. PSOLUTION: In a multi-processor system constituted of cards (#0)1 and (#1)2, a cache status PE(Pseudo-Exclusive) showing such a status that a cache line size write is ready while the data are invalid is newly added to a cache status MESI, and a protocol on the system interface for shifting to this status is decided. In the case of a pre-fetch operation for cache line size write in the multi-processor system, it can be instantaneously implemented on its own cache memory without reading from the main storage 4 or the fetching the data from a cache memory on another card. PCOPYRIGHT: (C)2007,JPO&INPIT
机译:

要解决的问题:提供一种多处理器系统,用于降低主存储器访问频率,降低请求代理程序的DA访问频率以及降低系统接口的数据传输频率。

解决方案:在由卡(#0)1和(#1)2构成的多处理器系统中,高速缓存状态PE(伪专有)显示这样的状态:在数据写入时,高速缓存行大小已准备就绪将无效的新添加到高速缓存状态MESI,并确定系统接口上用于转移到该状态的协议。在对多处理器系统中的缓存行大小进行写的预取操作的情况下,它可以立即在其自己的缓存中实现,而无需从主存储器4读取或从另一张卡上的缓存中获取数据。

版权:(C)2007,日本特许厅&INPIT

著录项

  • 公开/公告号JP2006330947A

    专利类型

  • 公开/公告日2006-12-07

    原文格式PDF

  • 申请/专利权人 NEC COMPUTERTECHNO LTD;

    申请/专利号JP20050151727

  • 发明设计人 SHIMADA SHINICHI;

    申请日2005-05-25

  • 分类号G06F12/08;

  • 国家 JP

  • 入库时间 2022-08-21 21:09:07

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