Being the sample/hold circuit which treats the output signal of the electric charge voltage converter in the Drive mannered null electric charge

摘要

PURPOSE: To provide a signal processing circuit capable of reducing the fluctuation of a signal level due to noise components caused by operations of other circuits in the same chip. CONSTITUTION: In a sample-and-hold circuit 10, a first hold capacitor 13 is connected in between a signal line L1 and a power source Vdd line and a seconded hold capacitor 14 is connected in between the signal line L1 and the ground. Then, the capacitance value of the capacitor for a sample-and-hold capacitor is evenly bisected into the first and the second capacitors 13, 14 to be replaced by them.