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Concurrent development assistance program of the programmable logic devices and ASIC, development support system development and support method
Concurrent development assistance program of the programmable logic devices and ASIC, development support system development and support method
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机译:可编程逻辑器件和ASIC的并发开发辅助程序,开发支持系统开发和支持方法
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摘要
A method for developing integrated circuits includes generating a core (logic core) in an HDL format readable by a logic synthesis tool, from an ASIC core (logic core) made of ports of blocks and port connection information, creating a temporary chip design from chip terminal information to generate a terminal in the temporary chip design, generating a design identical to that created, as a cell within the design created, connecting a design port with a cell port, wherein a name of the design port is identical to a name of the cell port, inserting an I/O buffer, depending on the device technology, into a net between the ports connected, replacing the cell by the core (logic core) created to generate a netlist, and expanding a hierarchy of the design, being the top hierarchy.
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