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Method and apparatus for delaying a load miss flush until issuing the dependent instruction
Method and apparatus for delaying a load miss flush until issuing the dependent instruction
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机译:延迟负载丢失刷新直到发出相关指令的方法和装置
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摘要
A pipeline processor has circuits to detect the presence of a register access instruction in an issue stage of the pipeline. A load-miss occurring at a later stage may cause the register access instruction to be marked with an associated bit. The register access instruction progresses down the pipeline and when the flush stage is reached, the processor checks the associated bit and flushes the register access instruction.
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