High-speed TDF testing on low cost testers using on-chip pulse generators and dual ATE references for rapidchip and ASIC devices

摘要

A circuit which facilitates TDF testing without having to purchase expensive new test equipment, such as a new test platform that is capable of supporting test frequencies well beyond the current 200 MHz limitation. A solution to current TDF testing problems by adding circuitry to the device-under-test (DUT) that is configured to receive two reference clock signals from automated test equipment (ATE), i.e. conventional ATE which does not provide test frequencies beyond 200 Mhz, and create two high-speed clock pulses that serve as the launch and capture clocks for the TDF test sequence on the DUT.