Methods of using ant colony optimization to pack designs into programmable logic devices

摘要

Methods of packing a design into a programmable logic device (PLD) using ant colony optimization. An augmented graph is assigned to the design, e.g., nodes and edges are defined based on sub-circuits and interconnections in the design, and a topological order is assigned to the nodes. An equation is determined for probabilistic behavior of packing agents at each node, and an initial pheromone value is assigned to each edge. In each iteration, each of “M” packing agents makes a tour of the graph, with merging decisions being made at each node in a probabilistic manner determined by the equation and pheromone values. The M resulting packing implementations are scored, and the best packing implementation is used to change the pheromone values for the next iteration. The probabilistic equation and scoring can be based on timing, area, and/or power constraints, for example. The process is complete when predefined criteria are met.