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Highly configurable PLL architecture for programmable logic
Highly configurable PLL architecture for programmable logic
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机译:高度可配置的PLL架构,用于可编程逻辑
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摘要
A programmable logic device includes configurable phase-locked loop (PLL) circuitry that outputs multiple clock signals having programmable phases and frequencies. Each output signal is programmably selectable for use as an external clock, internal global clock, internal local clock, or combinations thereof. The PLL circuitry has programmable frequency dividing, including programmable cascaded frequency dividing, and programmable output signal multiplexing that provide a high degree of clock design flexibility.
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