Multiprocessor system having shared buses, prioritized arbitration, and clock synchronization circuitry

摘要

A multiprocessor system having a plurality of processor elements each of which obtains right to use bus of a first or second shared bus in response to a transfer request for control system data or input/output data and as a master, conducts multiplex-transfer or burst-transfer, in which the processor element outputs a bus request signal for the first shared bus in response to a transfer request for the control system data and as a master, transfers and outputs a selection signal, a control signal and an address signal of a transfer destination and the control system data in one cycle in response to application of a bus grant signal, and is selected as a slave based on the selection signal through the first shared bus to receive input of the control system data and process the data based on the control signal and the address signal.