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Direct processor cache access within a system having a coherent multi-processor protocol

机译:具有一致的多处理器协议的系统内的直接处理器高速缓存访​​问

摘要

A computer system has a plurality of processors in a multiprocessor system with each processor associated with a cache memory. The cache traffic is monitored by the respective processors to determine the load for each of the cache memories. Signals corresponding to the cache loads are generated and analyzed. A target processor is selected for a push data operation from a bus agent to the cache memory using the load information. The push operations to the caches are optimized based on the cache traffic information.
机译:计算机系统在多处理器系统中具有多个处理器,每个处理器与高速缓存存储器相关联。高速缓存通信量由相应的处理器监视,以确定每个高速缓存存储器的负载。生成并分析与高速缓存负载相对应的信号。使用负载信息,选择目标处理器以用于从总线代理到高速缓存存储器的推送数据操作。根据缓存流量信息优化对缓存的推送操作。

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