VITERBI DECODER AND METHOD FOR DECIDING DATA BIT WIDTH OF THE ADD-COMPARE-SELECT UNIT THEREOF

摘要

The present invention relates to a Viterbi decoder, and a method for deciding minimal data bit width of add-compare-select unit, so as to reduce realization area of hardware of the Viterbi decoder and delay time of key path of the add-compare-select unit; it is effectively resolve overflow of PM value, and is generally suitble for parallel /serial/mixed type construction, it includes: the first step, span S_PM of path metric value(PM) of each column of the grid chart is calculated by the first expression ,i.e. S_PM≤n0·(m-1)·(2width-1); the second step, value of i is determined by the second expression, i.e,2i-2≤S_PM2i-1; the third step,it checks whether value of i meets with the third expression, i.e.(2i-1-1)+S_PM+ ·(2width-1)2i, if value of i meets the third expression, the minimal data bit width of add-compare-select unit is i bits; if value of i doesn’t meet with the third expression, the minimal data bit width of add-compare-select unit is( i+1) bits.