Flash memory architecture implementing simultaneously programmable multiple flash memory banks that are host compatible

摘要

A flash memory unit comprises a plurality of memory banks capable of simultaneously programming a plurality of pages into a plurality of data blocks within the respective memory banks. On start up, the flash memory System sends a signal to a host. If the host fails to respond, the flash memory unit determines that the host is a standard host and stores data one page at a time. If the host responds with a proper signal, the flash memory unit determines that the host is a high performance host and stores multiple pages of data simultaneously. The high performance host is configured to select identical LBA offsets from a plurality of virtual logical blocks of user data, and send the data defined by these logical block addresses to the flash memory unit for storage. The plurality of logical blocks of data are respectively transmitted to a plurality of RAM data registers, and simultaneously programmed into their respective memory banks. In sequential steps of programming, data defined by consecutive logical block addresses are stored in physical pages defined by consecutive physical block addresses. Data stored by a high performance host is therefore retrievable by a standard host.